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Электронный компонент: HT1620

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HT1625
RAM Mapping 648 LCD Controller for I/O mC
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Crystal Osc.
1
April 21, 2000
Features
Operating voltage: 2.7V~5.2V
Built-in RC oscillator
External 32.768kHz crystal or 32kHz
frequency source input
1/4 bias, 1/8 duty, frame frequency is 64Hz
Max. 648 patterns, 8 commons, 64 segments
Built-in internal resistor type bias generator
3-wire serial interface
8 kinds of time base/WDT selection
Time base or WDT overflow output
Built-in LCD display RAM
R/W address auto increment
Two selectable buzzer frequencies
(2kHz/4kHz)
Power down command reduces power
consumption
Software configuration feature
Data mode and Command mode instructions
Three data accessing modes
VLCD pin to adjust LCD operating voltage
Cascade application
General Description
HT1625 is a peripheral device specially de-
signed for I/O type mC used to expand the dis-
play capability. The max. display segment of
the device are 512 patterns (648). It also sup-
ports serial interface, buzzer sound, Watchdog
Timer or time base timer functions. The
HT1625 is a memory mapping and
multi-function LCD controller. The software
configuration feature of the HT1625 make it
suitable for multiple LCD applications includ-
ing LCD modules and display subsystems. Only
three lines are required for the interface be-
tween the host controller and the HT1625. The
HT162X series have many kinds of products
that match various applications.
Block Diagram
Pin Assignment
HT1625
2
April 21, 2000
T 2
C S
V S S
V L C D
T 1
T 3
SE
G
2
SE
G
0
SE
G
1
SE
G
3
SE
G
6
H T 1 6 2 5
1 0 0 Q F P
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
9 6
9 7
9 8
9 9
1 0 0
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
I R Q
SE
G
4
SE
G
5
SE
G
7
SE
G
8
SE
G
9
SE
G
1
0
SE
G
1
1
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
S E G 1 7
S E G 1 8
SE
G
4
8
SE
G
5
6
SE
G
5
5
SE
G
5
4
SE
G
5
3
SE
G
5
2
SE
G
5
1
SE
G
5
0
SE
G
4
9
SE
G
5
7
SE
G
4
7
SE
G
4
6
SE
G
4
5
SE
G
4
4
S E G 4 3
N C
S E G 4 2
S E G 4 1
S E G 4 0
S E G 3 9
S E G 2 0
S E G 1 9
SE
G
6
1
SE
G
6
0
SE
G
5
9
SE
G
5
8
O S C I
N C
N C
CO
M
7
NC NC
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
SE
G
6
3
SE
G
6
2
S E G 3 8
S E G 3 7
S E G 3 6
S E G 3 5
S E G 3 4
S E G 3 3
S E G 3 2
S E G 3 1
S E G 3 0
S E G 2 9
S E G 2 8
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 7
B Z
B Z
O S C O
V D D
R D
W R
D A T A
C O M 0
C O M 1
C O M 2
C O M 3
N C
N C
N C
N C
N C
C O M 4
C O M 5
C O M 6
N C
N C
N C
W a t c h d o g T i m e r
a n d
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C I
C S
R D
C O M 0
C O M 7
S E G 0
S E G 6 3
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
V S S
V D D
V L C D
I R Q
O S C O
Pad Assignment
Chip size: 192 211 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1625
3
April 21, 2000
CS
1
4 5
2
4 6
3
4 7
4
4 8
5
4 9
6
5 0
7
5 1
8
5 2
9
5 3
1 0
5 4
1 1
5 5
1 2
5 6
1 3
5 7
1 4
5 8
1 5
5 9
1 6
6 0
1 7
6 1
1 8
6 2
1 9
6 3
2 0
6 4
2 1
6 5
2 2
6 6
2 3
6 7
2 4
6 8
2 5
6 9
2 6
7 0
2 7
7 1
2 8
7 2
2 9
7 3
3 0
7 4
3 1
7 5
3 2
7 6
3 3
7 7
3 4
7 8
3 5
7 9
3 6
8 0
3 7
8 1
3 8
8 2
3 9
8 3
4 0
8 4
4 1
8 5
4 2
8 6
4 3
8 7
4 4
( 0 , 0 )
D A T A
V S S
O S C O
O S C I
V D D
V L C D
B Z
T 1
T 2
T 3
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
CO
M
5
CO
M
6
CO
M
7
SE
G
0
SE
G
1
SE
G
2
SE
G
3
SE
G
4
SE
G
5
SE
G
6
SE
G
7
SE
G
8
SE
G
9
SE
G
1
0
SE
G
1
1
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
SE
G
1
7
SE
G
1
8
SE
G
1
9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 5
S E G 2 4
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
S E G 3 2
S E G 3 3
S E G 3 4
S E G 3 5
S E G 3 6
S E G 3 7
S E G 3 8
S E G 3 9
S E G 4 0
S E G 4 1
S E G 4 2
SE
G
4
3
SE
G
4
4
SE
G
4
5
SE
G
4
6
SE
G
4
7
SE
G
4
8
SE
G
4
9
SE
G
5
0
SE
G
5
1
SE
G
5
2
SE
G
5
3
SE
G
5
4
SE
G
5
5
SE
G
5
6
SE
G
5
7
SE
G
5
8
SE
G
5
9
SE
G
6
0
SE
G
6
1
SE
G
6
2
SE
G
6
3
R D
W R
I R Q
B Z
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
-90.18
98.56
45
90.57
-84.53
2
-90.18
91.93
46
90.57
-77.90
3
-90.18
85.30
47
89.80
-68.13
4
-90.18
75.95
48
89.80
-61.50
5
-89.42
57.76
49
89.80
-49.51
6
-89.42
45.77
50
89.80
-42.88
7
-90.18
39.14
51
89.80
-30.90
8
-90.18
32.51
52
89.80
-24.27
9
-90.18
25.03
53
89.80
-12.28
10
-90.18
15.94
54
89.80
-5.65
11
-90.18
5.82
55
89.80
6.33
12
-90.18
-3.61
56
89.80
12.96
13
-90.18
-10.24
57
89.80
24.95
14
-90.18
-16.87
58
89.80
31.58
15
-90.18
-23.50
59
89.80
43.56
16
-90.18
-30.13
60
89.80
50.19
17
-90.18
-36.76
61
89.80
62.18
18
-90.18
-43.39
62
89.80
68.81
19
-90.18
-92.22
63
89.80
80.79
20
-83.17
-99.53
64
89.80
87.42
21
-76.54
-99.53
65
89.38
98.22
22
-69.91
-99.53
66
77.39
98.22
23
-63.28
-99.53
67
70.76
98.22
24
-56.65
-99.53
68
58.78
98.22
25
-50.02
-99.53
69
52.15
98.22
26
-43.39
-99.53
70
40.16
98.22
27
-36.76
-99.53
71
32.09
99.32
28
-30.13
-99.53
72
25.46
99.32
29
-23.50
-99.53
73
18.83
99.32
30
-16.87
-99.53
74
12.20
99.32
31
-10.24
-99.53
75
5.57
99.32
32
-3.61
-99.53
76
-1.06
99.32
33
3.02
-99.53
77
-7.69
99.32
34
9.65
-99.53
78
-14.32
99.32
35
16.28
-99.53
79
-20.95
99.32
36
22.91
-99.53
80
-27.58
99.32
37
29.54
-98.60
81
-34.21
99.32
38
41.52
-98.60
82
-40.84
99.32
39
48.15
-98.60
83
-47.47
99.32
40
60.14
-98.60
84
-54.10
99.32
41
66.77
-98.60
85
-60.73
99.32
42
78.75
-98.60
86
-67.36
99.32
43
90.57
-97.79
87
-73.99
99.32
44
90.57
-91.16
HT1625
4
April 21, 2000
Pad Description
Pad No.
Pad Name
I/O
Description
1
RD
I
READ clock input with pull-high resistor. Data in the RAM of the
HT1625 are clocked out on the rising edge of the RD signal. The
clocked out data will appear on the data line. The host controller
can use the next falling edge to latch the clocked out data.
2
WR
I
WRITE clock input with pull-high resistor. Data on the DATA
line are latched into the HT1625 on the rising edge of the WR sig-
nal.
3
DATA
I/O Serial data input/output with pull-high resistor
4
VSS
Negative power supply, Ground
5
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal
in order to generate a system clock. If the system clock comes
from an external clock source, the external clock source should be
connected to the OSCI pad. But if an on-chip RC oscillator is se-
lected instead, the OSCI and OSCO pads can be left open.
6
OSCO
O
7
VDD
Positive power supply
8
VLCD
I
LCD operating voltage input pad.
9
IRQ
O Time base or Watchdog Timer overflow flag, NMOS open drain
output
10, 11
BZ, BZ
O 2kHz or 4kHz tone frequency output pair
12~14
T1~T3
I
Not connected
15~22
COM0~COM7
O LCD common outputs
23~86
SEG0~SEG63
O LCD segment outputs
87
CS
I
Chip selection input with pull-high resistor. When the CS is logic
high, the data and command read from or write to the HT1625
are disabled. The serial interface circuit is also reset. But if the
CS is at logic low level and is input to the CS pad, the data and
command transmission between the host controller and the
HT1625 are all enabled.
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50C to 125C
Input Voltage................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.
HT1625
5
April 21, 2000